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PIC18F66K80 FAMILY

DS39977F-page 216

2010-2012 Microchip Technology Inc.

14.7

Resetting Timer1 Using the ECCP

Special Event Trigger

If ECCP modules are configured to use Timer1 and to

generate a Special Event Trigger in Compare mode

(CCP1M<3:0> = 1011), this signal will reset Timer1. The

trigger from ECCP will also start an A/D conversion if the

A/D module is enabled. (For more information, see

Section 20.3.4 “Special Event Trigger”

To take advantage of this feature, the module must be

configured as either a timer or a synchronous counter.

When used this way, the CCPR1H:CCPR1L register

pair effectively becomes a Period register for Timer1.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

Special Event Trigger, the write operation will take

precedence.

14.8

Timer1 Gate

Timer1 can be configured to count freely or the count can

be enabled and disabled using the Timer1 gate circuitry.

This is also referred to as Timer1 gate count enable.

Timer1 gate can also be driven by multiple selectable

sources.

14.8.1

TIMER1 GATE COUNT ENABLE

The Timer1 Gate Enable mode is enabled by setting

the TMR1GE bit of the T1GCON register. The polarity

of the Timer1 Gate Enable mode is configured using

the T1GPOL bit (T1GCON<6>).

When Timer1 Gate Enable mode is enabled, Timer1

will increment on the rising edge of the Timer1 clock

source. When Timer1 Gate Enable mode is disabled,

no incrementing will occur and Timer1 will hold the

current count. See Figure 14-4 for timing details.

TABLE 14-3:

TIMER1 GATE ENABLE

SELECTIONS

Note:

The Special Event Trigger from the ECCP

module will only clear the TMR1 register’s

content, but not set the TMR1IF interrupt

flag bit (PIR1<0>).

T1CLK()

T1GPOL

(T1GCON<6>)

T1G Pin

Timer1

Operation

Counts

Holds Count

Counts

The clock on which TMR1 is running. For more

information, see Figure 14-1.

Note:

The CCP and ECCP modules use Timers,

1 through 4, for some modes. The assign-

ment of a particular timer to a CCP/ECCP

module is determined by the Timer to CCP

enable bits in the CCPTMRS register. For

more details, see Register 20-2 and

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